COLECO ADAM TECHNICAL MANUAL

Coleco makes no representations or warranties whatsoever, including without limitation any implied warranties of merchantability and fitness for a particular purpose, in connection with the materials contained herein, and such materials are disclosed as is. Coleco shall have no liability for any losses caused to recipients of these materials by reason of any changes or modifications made by Coleco in these materials after their disclosure herein, in addition, Coleco shall have no liability for any consequential, special, indirect or incidental damages or losses whatsoever, including loss of profits, in connection with the use of the materials disclosed herein.

© 1984 Coleco Industries, Inc.

All rights reserved

ADAMTM, SmartBasicTM, SmartWRITERTM, and AdamNETTM are trademarks of Coleco Industries, Inc. ColecoVision® is a registered trademark of Coleco Industries, Inc. Buck RogersTM indicates a trademark of the Dillie Family Trust © 1982 The Dille Family Trust. Planet of ZoomTM and SEGA® are trademarks of SEGA Enterprises, Inc. © 1982 SEGA Enterprises, Inc.


ADAMTM
TECHNICAL REFERENCE MANUAL

PRELIMINARY RELEASE

COLECO INDUSTRIES, INC.


ACKNOWLEDGEMENTS

Editor: Maria Higgini
Technical Consultants: Brian Taylor
David K. Hwang
Robert Jepson
Cover Design: Laura Shea

COLECO MAKES NO REPRESENTATIONS OR WARRANTIES WHATSOEVER, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, IN CONNECTION WITH THE MATERIALS CONTAINED HEREIN, AND SUCH MATERIALS ARE DISCLOSED AS IS. COLECO SHALL HAVE NO LIABILITY FOR ANY LOSSES CAUSED TO RECIPIENTS OF THESE MATERIALS BY REASON OF ANY CHANGES OR MODIFICATIONS MADE BY COLECO IN THESE MATERIALS AFTER THEIR DISCLOSURE HEREIN. IN ADDITION, COLECO SHALL HAVE NO LIABILITY FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT OR INCIDENTAL DAMAGES OR LOSSES WHATSOEVER, INCLUDING LOSS OF PROFITS, IN CONNECTION WITH THE USE OF THE MATERIALS DISCLOSED HEREIN.

© 1984 Coleco Industries, Inc.

All rights reserved

ADAMTM, SmartBasicTM, SmartWRITERTM, and AdamNETTM are trademarks of Coleco Industries, Inc. ColecoVision® is a registered trademark of Coleco Industries, Inc. Buck RogersTM indicates a trademark of the Dillie Family Trust © 1982 The Dille Family Trust. Planet of ZoomTM and SEGA® are trademarks of SEGA Enterprises, Inc. © 1982 SEGA Enterprises, Inc.


PREFACE

The ADAM Family Computers System Technical Reference Manual is a source of technical information for both hardware and software designers. This preliminary release of the manual includes the most essential information.

Section I, Functional Description, covers all the function blocks of the system. Included are the essentials for understanding the hardware architecture and information on each of ADAM's software components.

Section II, EOS User's Manual, supplies the necessary information for using the Elementary Operating System.

Section III, Optional Peripherals, contains notes about the differences between the disk drive and the tape drive and source listings for the AdamLink MODEM.

Section IV, EOS_6 Absolute Listings, supplies listings for Elementary Operating System.

Section V, OS_7 Absolute Listings, supplies listings for OS_7 code.


TABLE OF CONTENTS

Preface

Section I:  Functional Description

  Chapter 1:  General Introduction

    1.  Hardware Overview
    2.  Software Overview

      Fig. 1-3  ADAM Software Architecture

  Chapter 2:  Hardware

    1.  Introduction

      Fig. 2-1  System Block Diagram
      Fig. 2-2  System Flow Diagram

    2.  The Memory Console

      2.1  The Memory and I/O Printed Circuit Board

        2.1.1  Theory of Operation

          Fig. 2-3  Memory and I/O Board Block Diagram

        2.1.2  Master 6801 Microcomputer
        2.1.3  Memory Input/Output Controller (MIOC)
        2.1.4  ROM Circuitry
        2.1.5  Dynamic RAM Circuitry
        2.1.6  AdamNet Interface Circuitry
        2.1.7  Card-Edge Expansion Connectors

          2.1.7a  Connector #1
          2.1.7b  Connector #2
          2.1.7c  Connector #3

        2.1.8  Expansion Port

        Table 1:  DC Characteristics
        Table 2:  Timing Reference Table

        2.1.9  Interconnects

          2.1.9a  Memory and I/O Board/CPU Board
          2.1.9b  Interconnects for Connector #1 at J7
          2.1.9c  Interconnects for Connector #2 at J6
          2.1.9d  Interconnects for Connector #3 at J5
          2.1.9e  Other Memory and I/O Board Connections

        Table 3:  Cartridge Interface Parameters

      2.2  The CPU Board

        2.2.1  Theory of Operation

          Fig. 2-4  Block Diagram: CPU Board

        2.2.2  Z80 Microprocessor
        2.2.3  ROM Circuitry
        2.2.4  Video Display Processor
        2.2.5  Sound Generator
        2.2.6  RF Circuitry
        2.2.7  Game Controller Circuitry
        2.2.8  Clock Generation
        2.2.9  Interconnects

      2.3  Data Pack Drive

        2.3.1  Theory of Operation
        2.3.2  Servo Printed Circuit Board
        2.3.3  Read Write Printed Circuit Board
        2.3.4  Data Pack Specifications
        2.3.5  I/O Signals between Memory and I/O Board
               and Data Drive

      2.4  Differences of Expansion Module 3

    3.  The Keyboard

      3.1  Theory of Operation
      3.2  Interconnects

    4.  The Printer

      4.1  Theory of Operation
      4.2  Printer Board
      4.3  Interconnects

    5.  Game Controllers

      Fig. 2-5  Game Controller Configuration

    6.  Power Supply

      6.1  Power Supply Voltage
      6.2  Excessive Current Output Protection
      6.3  Printer/Memory Console Interface Cable
      6.4  Power Supply Output to CPU (via Printer/
           Memory Console Interface Cable)
      6.5  Power Supply Output to Printer

  Chapter 3:  Software

    1.  Introduction
    2.  Memory Map and Power Up/Reset Procedure

      2.1  Lower Memory Options
      2.2  Upper Memory Options
      2.3  Power Up/Computer Reset Procedures
      2.4  Z80 I/O Port Assignments
      2.5  Memory Map Control
      2.6  Reset Procedures

    3.  AdamNet

      3.1  Introduction

        Fig. 3-1  Bus Network

      3.2  Logical Design

    4.  Operating System

      4.1  EOS

        Fig. 3-4  EOS Memory Map
        4.1.1  EOS Overwrite Addresses
        4.1.2  EOS Files

    5.  Tape Format and Other Tape Considerations

      5.1  Considerations in Choosing Tape Format

    6.  SmartWRITER

      6.1  Memory Map
      6.2  SmartWRITER-Compatible Files

    7.  SmartBASIC

  Chapter 4:  [unknown; not present]

  Chapter 5:  Development Tools and Utilities

    1.  Super Games

      1.1  Background Loading
      1.2  Timing Considerations
      1.3  Mapping

        1.3.1  Overlay Control Blocks

      1.4  Start of Game
      1.5  8000H Area Code - Interface to Cold Start Loader
      1.6  Tape Interface Software

        1.6.1  Tape Manager Program
        1.6.2  TAPE_INTERFACE

      1.7  Background Loading Software
      1.8  TAPE_MANAGER
      1.9  TAPE_INTERFACE
      1.10  DDP_MANAGER
      1.11  DDP_INTERFACE

  Appendix

    1.  Keyboard Table
    2.  ADAM Emulation Considerations
    3.  Program Cautions - NMI (Non-Maskable Interrupts)

      3.1  Deferral
      3.2  Bank Switching

    4.  Schematics and Component Location/Identification
        Drawings

      4.1  Memory and I/O Board

        4.1.1  Memory and I/O Board Schematic, Sheet 1
        4.1.2  Memory and I/O Board Schematic, Sheet 2
        4.1.3  Memory and I/O Board Component Location/
               Identification Drawing

      4.2  CPU Board

        4.2.1  CPU Board Schematic
        4.2.2  CPU Board Component Location/Identification
               Drawing

      4.3  Interconnect Board

        4.3.1  Interconnect Board Schematic
        4.3.2  Interconnect Board Component Location/
               Identification Drawing

      4.4  Linear Power Supply

        4.4.1  Linear Power Supply Schematic
        4.4.2  Linear Power Supply Component Location/
               Identification Drawing
        4.4.3  Linear Power Supply Sub-Assembly

Section II:  EOS User's Manual

Section III:  Optional Peripherals

Section IV:  EOS-6 Absolute Listings

Section V:  OS-7 Absolute Listings



SECTION I

ADAM - FUNCTIONAL DESCRIPTION


CHAPTER 1: GENERAL INTRODUCTION

1.  Hardware Overview

The ADAM Family Computer System consists of three major components: the memory console, the keyboard, and the printer. The consumer provides his own TV or monitor. Other equipment provided with the system are two "joystick" game controllers, various cords and cables to connect the components, and an antenna switch box.

The memory console houses the main memory and the CPU of the system, and one data pack drive. Space and connectors are provided for another drive. Two printed circuit boards contain 64K RAM, 16K video RAM, and expansion port, two AdamNet ports, three card connectors and a cartridge slot. Two additional printed circuit boards control the drives.

The system reads from and stores on digital data packs. Digital data packs are a reel to reel magnetic tape encased in a LexanTM cassette, Each data pack can store up to 256K bytes.

The keyboard has 75 full travel keys, including ten command keys and six programmable function keys. A "power on" LED indicator on the right side of the keyboard shows when the system is on. The keyboard contains one printed circuit board.

The printer is a letter-quality, bi-directional, daisy wheel printer. Paper feeds into the printer through a friction-feed mechanism that accommodates single sheets of paper up to 9-1/2 inches wide. With the addition of an optional tractor-feed mechanism, the printer also accommodates continuous, "fan-fold" paper. Pitch is 10 characters to the inch, and printing speed is 10 characters per second. The printer contains two printed circuit boards, one for the printer and one for the power supply.

The computer's power supply, which produces 4 regulated DC voltages, is housed in the printer.

ADAM is available in two models, the complete system and Expansion Module #3. When the memory console of Expansion Module #3 is connected to ColecoVision, the two models are essentially identical in function.

The block diagram in Figure 2-1 represents a high-level view of the system's hardware design. The major elements in the block diagram are discussed in greater detail in Chapter 2, Hardware.

2.  Software Overview

ADAM's hardware components are linked together by a 62.5K bps, half-duplex, shared serial bus, known as AdamNet.

EOS (Elementary Operating System) is a collection of service routines that provides input and output facilities to peripheral devices, in such a way that the application programs need not address the physical characteristics of the peripherals or the operation of AdamNet. EOS also provides file management for manipulating data on mass storage devices.

OS-7 is a run-time user's library of software modules that control graphics, sound, timing, etc. EOS contains many modules equivalent to OS-7 modules, but some have different inputs and outputs.

ADAM contains a ROM-based electric typewriter/word processor/editor called SmartWRITER. SmartBASIC and the Buck RogersTM Planet of ZoomTM Super Game are included with Adam on data packs.

Each of ADAM's software components is discussed in greater detail in Chapter 3. Figure 1-3 depicts Adam's software architecture.

[FIGURE 1-3: ADAM SOFTWARE ARCHITECTURE]


CHAPTER 2: HARDWARE

1.  Introduction

This chapter presents technical information on each of the major logical components of ADAM identified in the System Block Diagram, Figure 2-1. The Appendix contains schematics and component location/identification drawings.

For the convenience of hardware developers, pin and signal connections for all expansion connectors are given. The Memory Console provides a total of four expansion connectors. Three female card edge connectors are accessed by removing the top cover of the Memory Console. These are referred to as expansion connectors #1, #2, and #3. One male card edge connector extends from the right side of the Memory Console. This is referred to as the Expansion Port.

[FIGURE 2-1: SYSTEM BLOCK DIAGRAM]

[FIGURE 2-2: SYSTEM FLOW DIAGRAM]

2.  THE MEMORY CONSOLE

2.1  The Memory and I/O Printed Circuit Board

2.1.1  Theory of Operation

The Memory and I/O Board contains the 6801 Master microcomputer, 72K bytes of RAM and provisions for up to 72 K of ROM/EPROM. This board provides the circuitry required to interface the keyboard, printer, tape drive, and future options. Three card-edgem connectors profice access for future options. An expansion port provides access for external peripherals. A custom LSI circuit, the Memory Input Output Controller (MIOC), interfaces the 6801 Master microcomputer with the Z80 microprocessor on the CPU Board. Another 6801 microcomputer on the Memory and I/O Board controls the operation of the tape drive interface circuitry.

[FIGURE 2-3: THE MEMORY AND I/O BOARD BLOCK DIAGRAM]

2.1.2  The Master 6801 Microcomputer

The Master 6801 microcomputer's primary function is to control system access to the keyboard, printer, tape drive, and future peripherals. The Master 6801 microcomputer is a front-end network processor that supports the Z80. The Master 6801 communicates with the Z80 via the Memory Input Output Controller. The Master 6801 reads and writes information to and from network peripherals on command by the Z80.

The 6801 chip provides 2048 bytes of ROM, 128 bytes of RAM, and a UART. The Master 6801 is configured for single chip mode operation and runs, as do Adam's other 6801s, at a 1 MHz rate. This frequency is derived from an external 4 MHz crystal and the 6801's internal divide-by-4 circuitry.

2.1.3  The Memory Input Output Controller (MIOC)

The Memory Input Output Controller is a 40-pin IC that interfaces two dissimilar microprocessors (the Z80 and the Master 6801) by performing the proper decoding and timing functions. It is responsible for selecting the memory configuration (Refer to Chapter 3, Section 2). The MIOC has 22 input signals, 16 output signals, power, and ground.

2.1.4  ROM Circuitry

Room is provided on the Memory and I/O Board for up to 40K of ROM. ROM selection is controlled by a decoder circuit which is driven by A13, /BOOTROMCS and /EOS_ENABLE. The Memory and I/O Board ROM circuit contains EOS (Elementary Operating System) software.

2.1.5  Dynamic RAM Circuitry

The dynamic RAM circuit consists of eight 64K RAM chips arranged so that each represents one specific data bus bit. Information written to or read from RAM is controlled by the /BWR, /RAS, and /CAS1 signals. The latched Z80 address bus BA0-BA15 (or BA0-BA6, RA7, BA8-BA15) is provided along with MUX from the MIOC to the two data selector multipexer, which provide MA0-MA7 (or RA7) to the DRAM address bus. Z80 provides a 7-bit refresh address after each instruction fetch. The MIOC generates an eighth bit for 256-refresh cycle dynamic RAMs. See Appendix 2, Adam Emulation Considerations, for further information.

2.1.6.  AdamNet Interface Circuitry

A quad comparator circuit provides data to and from the Master 6801 microcomputer via a half-duplex 62.5 kilobaud serial network called AdamNET. The comparator can also reset all the devices on AdamNET via MIOC control. AdamNET links the tape drive, printer, and keyboard to the Master 6801. Each of these peripherals has a 6801 and a quad comparator circuit that controls AdamNET. Besides the data signal and reset signal, ground and power are provided as part of the AdamNET bus.

2.1.7  Card Edge Expansion Connectors

Three card edge connectors are provided for future development. Refer to Subsection 2.1.9 for pin connections.

2.1.7a  Connector #1

This connector is soldered to the Memory and I/O Board, and is labelled J7.

2.1.7b  Connector #2

This connector is designed for expansion ROM and I/O devices and is soldered to the Memory and I/O Board. It is labelled J6.

2.7.1c  Connector #3

This connector allows for expansion RAM and/or ROM up to 64K bytes, and is labelled J5.

2.1.8  Expansion Port

The expansion port is connected to the Memory and I/O Board at P1.

Pin Type Refer To Table Pin Type Refer To Table
1 Ground   31 Audio input  
2 Ground   32 Video input enable +9 VDC  
3 BD3 Tristate, I/O 1, 2 33 NTSC composite video
input, 6 VDC, 1.5 VAC
 
4 BA14 Tristate output 1, 2 34 /GAME_MODE_RESET output  
5 Y2 LS138 decoder output   35 Sound chip 76489 disable, 0 VDC  
6 Y1 LS138 decoder output   36 Not in use  
7 /HALT input 1, 2 37 BA11 Tristate output 1, 2
8 /BWR Tristate output 1, 2 38 BA12 Tristate output 1, 2
9 /NMI input/output 1 39 VDP Sync/Reset input 1
10 /SPINNER_INT_DISABLE input 1 40 /BIORQ Tristate output  
11 /BUSRQ input 1 41 Not used  
12 BD1 Tristate, I/O 1, 2 42 Not used 1
13 /Z80_RESET input 1, 2 43 BA15 Tristate output 1, 2
14 BD0 Tristate, I/O 1, 2 44 BA3 Tristate output 1, 2
15 /BM1 Tristate output 1, 2 45 BF 3.58 MHz clock  
16 BD7 Tristate, I/O 1, 2 46 BD2 Tristate, I/O 1, 2
17 BD6 Tristate, I/O 1, 2 47 BA0 Tristate output 1, 2
18 BA1 Tristate output 1, 2 48 BD5 Tristate, I/O 1, 2
19 BD4 Tristate, I/O 1, 2 49 /BRFSH Tristate output  
20 BA2 Tristate output 1, 2 50 /WAIT input 1, 2
21 BA4 Tristate output 1, 2 51 /INT input 1, 2
22 BA13 Tristate output 1, 2 52 /BUSAK output 1, 2
23 BA5 Tristate output 1, 2 53 /BRD Tristate output 1, 2
24 BA6 Tristate output 1, 2 54 /BMREQ Tristate output 1
25 BA7 Tristate output 1, 2 55 /IORQ output 1,2
26 BA8 Tristate output 1, 2 56 AUDIO 76489 RDY output  
27 BA9 Tristate output 1, 2 57 +12V  
28 BA10 Tristate output 1, 2 58 +5V  
29 /AUX_DECODE_1 input 1 59 +5V  
30 /AUX_DECODE_2 input 1 60 -5V  

/X - Denotes active low

TABLE 1: DC CHARACTERISTICS

Symbol Parameter Min Typ Max Units Test Conditions
VIL Input low voltage -0.3   0.8 V  
VIH Input high voltage 2.0   Vcc V  
VOL Output low voltage     0.4 V IOL = 1.8 mA
VOH Output high voltage 2.4     V IOH = 250 µA
ILI Input leakage current     ±10 µA VIN = 0 to Vcc
ILO Tri-state output
Leakage current in float
    ±10 µA VOUT = 0.4 V to Vcc

TABLE 2: TIMING REFERENCE TABLE

[ ]* See notes at end of table

SIGNAL SYMBOL PARAMETER MIN
(ns)
MAX
(ns)
A0-15

tD(AD)

tF(AD)

tacm

taci

tca

tcaf

Address output delay

Delay to float

Address stable prior to /MREQ (memory cycle)

Address stable prior to /IORQ, /RD, or /WR (I/O cycle)

Address stable from /RD, /WR, /IORQ, or /MREQ

Address stable from /RD or /WR during float

---

---

[1]*

[2]*

[3]*

[4]*

110

90

---

---

---

---

D0-7

tD(D)

tF(D)

tSF(D)

tSF(D)

tdcm

tdci

tdcf

tH

Data output delay

Delay to float during write cycle

Data setup time to rising edge of clock during M1 cycle

Data setup time to falling edge at clock during M2 to M5

Data stable prior to /WR (memory cycle)

Data stable prior to /WR (I/O cycle)

Data stable from /WR

Input hold time

---

---

35

50

[5]*

[6]*

[7]*

0

150

90

---

---

---

---

---

---

/MREQ

tDLF(MR)

tDHF(MR)

tDHF(MR)

tw(/MRL)

tw(/MRH)

/MREQ delay from falling edge of clock, /MREQ low

/MREQ delay from rising edge of clock, /MREQ high

/MREQ delay from falling edge of clock, /MREQ high

Pulse width, /MREQ low

Pulse width, /MREQ high

20

---

---

[8]*

[9]*

85

85

85

---

---

/IORQ

tDLF(IR)

tDLF(IR)

tDHF(IR)

tDHF(IR)

/IORQ delay from rising edge of clock, /IORQ low

/IORQ delay from falling edge of clock, /IORQ low

/IORQ delay from rising edge of clock, /IORQ high

/IORQ delay from falling edge of clock, /IORQ high

---

---

---

---

75

85

85

85

/RD

tDLF(RD)

tDLF(RD)

tDHF(RD)

tDHF(RD)

/RD delay from rising edge of clock, /RD low

/RD delay from falling edge of clock, /RD low

/RD delay from rising edge of clock, /RD high

/RD delay from falling edge of clock, /RD high

---

---

15

---

85

95

85

85

/WR

tDLF(WR)

tDLF(WR)

tDHF(WR)

tw(/WRL)

/WR delay from rising edge of clock, /WR low

/WR delay from falling edge of clock, /WR low

/WR delay from falling edge of clock, /WR high

Pulse width, /WR low

---

---

---

[10]*

65

80

80

---

/M1

tDLF(M1)

tDHF(M1)

/M1 delay from rising edge of clock, /M1 low

/M1 delay from rising edge of clock, /M1 high

---

---

100

100

/RFSH

tDLF(RF)

tDHF(RF)

/RFSH delay from rising edge of clock, /RFSH low

/RFSH delay from rising edge of clock, /RFSH high

---

---

130

120

/WAIT tS(WT) /WAIT setup time to falling edge of clock 70 ---
/HALT tD(HT) /HALT delay time from falling edge of clock --- 300
/INT tS(IT) /INT setup time to rising edge of clock 80 ---
/NMI tw(NMI) Pulse width, /NMI low 80 ---
/BUSRQ tS(BQ) /BUSRQ setup time to rising edge of clock 50 ---
/BUSAK

tDL(BA)

tDH(BA)

/BUSAK delay from rising edge of clock, /BUSAK low

/BUSAK delay from falling edge of clock, /BUSAK high

---

---

1xx

100

/RESET

tS(RS)

tF(C)

tmr

/RESET setup time to rising edge of clock

Delay to/from float (/MREQ, /IORQ, /RD, and /WR)

/M1 stable prior to /IORQ (interrupt ack.)

60

---

[11]*

---

x0

---

Timing Reference Table Notes

[1] tacm = tw(FH) + tf - 65
[2] taci = tc - 75
[3] tca = tw(FL) + tr - 50
[4] tcaf = tw(FL) + tr - 45
[5] tdcm = tc - 170
[6] tdci = tw(FL) + tr - 170
[7] tcdf = tw(FL) + tr - 70
[8] tw(/MRL) = tc - 30
[9] tw(/MRH) = tw(FH) + tf - 20
[10] tw(/WRL) = tc - 30
[11] tmr = 2tc + tw(FH) + tf - 65
  tc = clock period: 279.36 ns ± 0.01
  tw(FH) = clock pulse width, clock High = 120 ns min
  tw(FL) = clock pulse width, clock Low = 120 ns min
  tf = clock fall time = 15 ns max
  tr = clock rise time = 15 ns max

2.1.9  Interconnects

2.1.9a  Memory and I/O Board/CPU Board

The Memory and I/O Board is connected to the CPU board at J1, with two 30-pin ribbon cables and a dual 30-pin card edge connector.

BD0-BD7 8 bidirectional data lines. BD0 is least significant, BD7 is most significant.
BA0-BA15 16 address lines to Memory and I/O Board. BA0 is least significant, BA15 is most significant.
/BWR Output of Z80 to Memory and I/O Board; write strobe used to output data during an I/O or memory operation. Indicates a write operation.
/BRD Output of Z80 to Memory and I/O Board; read strobe used to clock data into the Z80 during an I/O or memory operation.
/BMREQ Output of Z80 to Memory and I/O Board; indicates present read or write operation is directed to memory or memory-mapped devices.
/IORQ
/BIORQ
Same as /BMREQ, but indicates an I/O operation instead of memory or memory-mapped devices.
/BRFSH Output of Z80 to Memory and I/O Board; indicates BA0-BA6 contain a row address for the required dynamic memory refresh. (An eighth row address bit is generated by the MIOC, 'RA7'.)
/RST Generated by the MIOC as a result of either a game /CVRST or computer /PBRST reset. It connects to and resets the ColecoVision or CPU Board.
BF System clock generated on ColecoVision or CPU Boards. Line connects to Memory and I/O Board.
/WAIT Used to insert extra clock cycles into Z80 timing during opcode fetch cycles and when accessing slow memory or I/O. Excessive use of /WAIT causes inadequate dynamic RAM refresh.
/ADDRBUFEN An active low signal enables the address and control signal buffers between the ColecoVision or CPU Board and the Memory and I/O Board. The control signals are /BRD, /BWR, /BRFSH, /BMREQ, /BM1, and /BIORQ. A high level disables these signals from the Z80, and allows them to go tristate (high-impedance). This occurs during a DMA cycle where another device needs to access memory or devices on the Memory and I/O Board. See /BUSRQ and /BUSAK.
/245EN Same as /ADDRBUFEN except /245EN controls the buffer for BD0 through BD7 data lines to CPU or ColecoVision buffer board.
/BUSRQ (unbuffered)
/BUSAK (buffered)
/BUSRQ is generated by the MIOC as the result of a DMA request. The /BUSRQ signal requests that the Z80 relinquish the address and data busses and certain control signals at the end of its current cycle. After receiving the /BUSRQ, the Z80 responds with a /BUSAK signal to indicate it has relinquished the bus. The Z80 remains in an inactive state until the controlling device removes the /BUSRQ signal. The /BUSRQ line connects to the ColecoVision or CPU Board. Generally, only the Master 6801 may assert a /BUSRQ.
/BM1 Output of Z80 from CPU or ColecoVision Board; indicates the present memory cycle is an opcode fetch (start of next instruction).
/CVRST This signal generates an /RST to the Z80 processor. Also reset are the MIOC and Master 6801. /CVRST initializes the MIOC memory map such that addresses from 0-1FFFH enable the OS-7 ROM; 2000H through 7FFFH enable RAM1; and 8000H through FFFFH enable the game cartridge.
/AUXDECODE1 Generated by Memory and I/O Board. Selects or deselects the OS-7 ROM.
/INT Active low, this signal is an input to the Z80 and results in a maskable interrupt which directs the Z80 to respond to some external event.
/SPINDIS Allows disabling of spinner interrupts by the hand controllers. Active low.
Audio Out
Audio In
AUX VID
VID GATE
CLK, /RSTDIS
SEL4, SEL2
/HALT, /NMI
/AUXDECODE2
/VIDRST
These signals are not used on the Memory and I/O Board but are made available at the expansion connector.
2.1.9b  Interconnects for Connector #1 at J7
BD0-BD7 8 bidirectional data lines. BD0 is least significant, BD7 is most significant.
BA0-BA7 8 address lines to Memory and I/O Board. BA0 is least significant, BA7 is most significant.
/BWR Output of Z80 to Memory and I/O Board; write strobe used to output data during an I/O or memory operation. Indicates a write operation.
/BRD Output of Z80 to Memory and I/O Board; read strobe used to clock data into the Z80 during an I/O or memory operation.
/IORQ
/BIORQ
Same as /BMREQ, but indicates an I/O operation instead of memory or memory-mapped devices. /IORQ is unbuffered; /BIORQ is buffered.
/BM1 Output of Z80 from CPU or ColecoVision Board; indicates the present memory cycle is an opcode fetch (start of next instruction).
/INT Active low, this signal is an input to the Z80 and results in a maskable interrupt, which directs the Z80 to respond to some external event.
2.1.9c  Interconnects for Connector #2 at J6
BD0-BD7 8 bidirectional data lines. BD0 is least significant, BD7 is most significant.
BA0-BA15 16 address lines to Memory and I/O Board. BA0 is least significant, BA15 is most significant.
/BWR Output of Z80 to Memory and I/O Board; write strobe used to output data during an I/O or memory operation. Indicates a write operation.
/BRD Output of Z80 to Memory and I/O Board; read strobe used to clock data into the Z80 during an I/O or memory operation.
/BMREQ Output of Z80 to Memory and I/O Board; indicates present read or write operation is directed to memory or memory-mapped devices.
/IORQ
/BIORQ
Same as /BMREQ, but indicates an I/O operation instead of memory or memory-mapped devices. /IORQ is unbuffered; /BIORQ is buffered.
/BM1 Output of Z80 from CPU or ColecoVision Board; indicates the present memory cycle is an opcode fetch (start of next instruction).
/INT Active low, this signal is an input to the Z80 and results in a maskable interrupt, which directs the Z80 to respond to some external event.
AUDIO_IN  
2.1.9d  Interconnects for Connector #3 at J5
BD0-BD7 8 bidirectional data lines. BD0 is least significant, BD7 is most significant.
BA0-BA15 16 address lines to Memory and I/O Board. BA0 is least significant, BA15 is most significant. RA7 is substituted for BA7.
/BWR Output of Z80 to Memory and I/O Board; write strobe used to output data during an I/O or memory operation. Indicates a write operation.
/BRD Output of Z80 to Memory and I/O Board; read strobe used to clock data into the Z80 during an I/O or memory operation.
2.1.9e  Other Memory and I/O Board Connections
J2 and J8 AdamNet Connections - The following signals are found on the AdamNet connectors for keyboard and expansion devices.
Data - 62.5K bps serial 'bidirectional' line for data transmission reception by network devices
Reset - hardware network reset
+5 V
Signal Ground
J9 Power Supply/Printer Connector - In addition to containing the signals found on J2 and J8, the necessary power supply voltages of +12 V logic, +12 V Inductive, and -5 V connect here.
J10 and J12 Data Drive Connectors - For a detailed description of the signals found on the data drive connectors, refer to Subsection 2.3.5.
J1 Cartridge Connector
Pin Type Pin Type Pin Type Pin Type Pin Type
1 D2 7 A0 13 RF ground 19 A13 25 A7
2 CS3* 8 D5 14 A11 20 A14 26 A9
3 D1 9 A1 15 A3 21 A5 27 CS4*
4 D3 10 D6 16 A10 22 CS2* 28 A8
5 D0 11 A2 17 A4 23 A6
6 D4 12 D7 18 CS1* 24 A12
29 Digital ground
30 +5 V Typical available current 0.2 A

*LS138 Decoder output. Refer to Table 3.

TABLE 3: CARTRIDGE INTERFACE PARAMETERS

Symbol Parameter Conditions Min Typ Max Units
VOH High level output voltage Vcc = Min, VIH = 2 V,
VIL = VIL Max, IOH = -400 µA
2.7 3.4   V
VOL Low level output voltage Vcc = Min, VIH = 2 V,
VIL = VIL Max
IOL = 8 mA   0.35 0.5 V
IOL = 4 mA   0.25 0.4 V
VIH High level input voltage   2     V
VIL Low level input voltage       0.8 V

2.2  THE CPU BOARD

2.2.1  Theory of Operation

The CPU Board, located in the console of the Adam computer system, consists of six major units: The Z80 Central Processing Unit (CPU), a Video Prcessor, an Audio Generator, the RF Modulator, Clock Generation and the Game Controller Section. The Z80 is the CPU of the entire computer system; all other microprocessors are slaves.

[FIGURE 2-4: CPU BOARD BLOCK DIAGRM]

2.2.2  Z80 Microprocessor

The Z80 CPU, which consists of a Z80A microprocessor and a clock circuit for synchronization, has control of the Adam computer system. The Z80 configures the memory map and can switch banks of memory. Refer to Chapter 3, Section 2 for details on the memory configuration.

2.2.3  ROM Circuitry

The CPU Board includes an 8K operating system ROM (OS-7) and a connector for up to 32K of cartridge ROM.

2.2.4  Video Display Processor (VDP)

The Video Display Processor, A Texas Instruments (TI) 9928, generates all video, control, and synchronization signals and controls the storage, retrieval, and refresh of display data in dynamic memory, VRAM. The 9928 uses a table-driven architecture that allows the programmer to control every pixel in the visual display area, and to define and control 32 "sprites". Sprites may be placed anywhere on the display and moved at will.

The VDP has three major interfaces: CPU, RF modulator, and VRAM. The VDP is addressable in data mode (used when VRAM is being written or read) and register mode (used when control information is being written to and read from one of the VDP's internal registers). The addresses of the ports in the CPU I/O address space are as follows:

Data Port 0BEH
Register Port 0BFH

The video RAM circuit consists of 8 (16384 x 1) RAM integrated circuits. The contents of VRAM define the TV image. A0, /CSW and /CSR and CPU-controlled input signals to the VDP that control when the data is written to or read from VRAM. The VDP output signals /R/W, /CAS, abd /RAS control the RAM operation.

Data can be transmitted to or from the CPU over the data bus, depending on the state of the Chip Select Write (/CSW) and Chip Select Read (/CSR) control lines. When /CSW is low, data is transmitted from the CPU to the Video Display Processor. When /CSR is low, data is transmitted from the Video Display Processor to the CPU. /CSR and /CSW should not be simultaneously low.

Another control line, address line A0, determines where the VDP retrieves or sends data. If A0 is in a high state, the data is stored into or retrieved from an internal register. The register used is determined by the data. If A0 is in a low state, the data is stored into or retrieved from the VRAM.

Refer to the Texas Instruments TMS9918A/TMS9928A/TMS9929A Video Display Processors Data Manual for further information.

2.2.5  Sound Generator

The system uses a TI 76489 (6496) sound generator controller to produce sounds. The chip contains three programmable tone generators, a programmable white-noise generator, and programmable attenuation for each of the channels. The chip is addressed through a single write-only port at location 0FFH. Wait-request hardware has been included in the system because the sound chip is a slow peripheral requiring data lines to be stable for a relatively long time while it is receiving data.

2.2.6  RF Circuitry

The RF modulator uses the 1889 chip to interface audio, color difference, and luminance signals to the antenna terminals of a TV receiver. It consists of two VHF channels, 3 or 4, selectable by a slide switch with determined LC tank circuits. The chroma subcarrier is derived from the 3.58 MHz system clock to ensure accuracy and stability. The sound oscillator's frequency modulator is achieved by using a 4.5 MHz tank circuit and deviating the center frequency via a varactor diode. Due to the incompatible signal level between the VDP 9928 and the 1889, a DC restoration circuit ensures the DC level of the video signal

The /R-Y, /B-Y, and Y signals from the VDP, along with the 3.58 MHz clock and the audio signal from the SN76489 (6496), are provided to the RF modulator to produce the composite video output.

2.2.7  Game Controller Circuitry

The two game controllers are connected to the CPU Board via two "D" type connectors. Each controller is accessed by the system through its own port. See CONT_SCAN in the OS-7 Source Code listing for details.

For each controller, 18 switches are read on a single 8-bit port. Therefore, once a port has been read, some decoding is required to determine which switches have been depressed.

Two spinner switches that are not wired in the controller are used in some games. To ensure that the spinner switch closures are processed as soon as they happen, they are connected to the CPU maskable interrupt, and the cartridge software determines which switch caused the interrupt.

Controller Connector Pin Out

Pin Type Comments
1 Indirect D0 input Refer to Table 1
2 Indirect D2 input Refer to Table 1
3 Indirect D3 input Refer to Table 1
4 Indirect D1 input Refer to Table 1
5 Strobe signal output, Common 1  
6 Indirect D6 input Refer to Table 1
7 Indirect D5 input Refer to Table 1
8 Strobe signal output, Common 0  
9 Indirect /INT input  

Strobe signal: typical 350 µsec pulse width, -0.7 V low, +2.8 V high typical.

For further information on the game controllers, refer to Chapter 2, Section 5.

2.2.8  Clock Generation

The system clock is a 3.58 MHz square wave generated by dividing the 7.12 MHz clock by two. The video chip clock (10.7 MHz) drives the Video Display Processor. The video chip clock is obtained from the third multiple, high-Q tuned tank circuit on the 3.58 MHz system clock. The 7.1 MHz clock is generated by a crystal-controlled oscillator. The output of the oscillator circit is buffered and divided by two to provide a 50% duty cycle wave form.

2.2.9  Interconnects

The CPU/Game Board and the Memory and I/O Board connect via two 30-pin ribbon cables and a dual 30-pin card edge connector, making a pin-for-pin connection between J1 on the Memory and I/O Board and J2 on the CPU Board. Refer to Subsection 2.1.9.

2.3  DATA PACK DRIVE MODULE

2.3.1  Theory of Operation

The data drive assembly provides for two drives: one is included with the system, the other is optional. The data drive is a computer-controlled, digital cassette drive.

The components of the data drive subsystem are located in two places: The Memory and I/O Board contains the tape drive 6801 microcomputer, a quad comparator, and RAM. The Read/Write and Servo Boards are located in the data drive assembly.

The data drive 6801 controls the direction of the tape, tape speed, stop, track selection, and the Read/Write operation. In addition, the data drive 6801 monitors the presence of a data pack and transmits and receives data through AdamNet.

The comparator interfaces the data drive 6801 to AdamNet. The RAM circuitry consists of two 1024 x 4 RAM integrated circuits, connected in parallel to provide an 8-bit data bus.

Two printed circuit boards, the Servo Board and the Read/Write board, are located in the data drive assembly.

2.3.2  The Servo Board

The Servo Board controls the direction and speed of the data drive by:

2.3.3  The Read/Write Board

The Read/Write Board records digital data enclosed in bi-phase mark format on two separate tracks on the tape. This board also plays back the data recorded on the two tracks, with data output in the same format as recorded. The data drive 6801 selects the tracks.

The bi-phase marke technique embeds the clock in the data line. When data is returned from the data drive to the data drive 6801, the data line is coded back to the standard binary format.

A "cassette-in-place" switch located on the data drive chassis lets the Servo Board know when the data pack is in place and ready for use. An optical encoding wheel interacts with the Servo Board and the tape for drive speed control.

2.3.4  Data Pack Specifications

The magnetic tape in the data pack is standard two-track digital recording tape, 300 feet in length by 0.15 inches in width.

Effective data transfer rate 1.4K bytes per second
Tape speed: Normal 20 inches per second
Tape speed: Fast forward/rewind 80 inches per second
Tape capacity Two tracks, 128 blocks per track, 1 block = 1K

2.3.5  I/O Signals between Memory and I/O Board and Data Drive

Signal Name Mem/I/O
Board
R/W I/O Description
BRAKE*
(input)
J10-1 E26 Brakes tape motion. Logic 1 (active high) applies brake. This signal is passed from the Read/Write (R/W) Board to the Servo Board at point E6.
/GO_REV
(input)
J10-2 E25 Commands reverse direction of tape motion when at Logic 0 (active low). This signal is passed from R/W Board to Servo Board at point Exx.
/GO_FWD
(input)
J10-3 E27 Commands forward direction of tape motion when at Logic 0 (active low). This signal is passed from R/W Board to Servo Board at point Exx.
STOP
(input)
J10-4 E28 Prevents tape motion and latches data drive output to Logic 1 when at Logic 1 (active high). Enables data drive output and tape motion when at Logic 0. This signal is used in circuits on both boards. It is passed from R/W board to Servo Board at point E9.
SPEED_SELECT
(input)
J10-5 E29 Selects speed of tape motion: Logic 0 = 20 ips (slow speed), Logic 1 = 80 ips (fast speed). This signal is passed from R/W Board to Servo Board at point E10.
GND J10-6 E30 Return path for all logic and analog signals. Connected from R/W Bord to Servo Board at point E19.
MSENSE
(output)
J10-7 E31 Provides sense of tape motion status for tape drive 6801 (active high). When Logic 1, tape is properly in motion. When Logic 0, tape is not moving due to stop/braking action or malfunction. This signal is passed between R/W Board and Servo Board as point Exx.
+12VI
(input)
J10-8 E32 +12 V Inductive Power Supply line, used to power motor circuitry. Passed from R/W to Servo circuit at point Exx.
/CIP
(output)
J10-9 E33 Indicates to tape drive 6801 that a data pack has been properly inserted in drive when Logic 0 (active low). Passed between R/W and Servo Boards at point E14.
DATA_IN
(input)
J11-1 E17 Data input to drive from tape drive 6801. Data is encoded in bi-phase mark format. Each bit cell is 70 µsec in duration. A logic 1 is denoted by a flux change in the bit cell. A logic 0 is denoted by no flux change in the bit cell. This data is input to the drive in a serial stream.
TRACK_A//B
(input)
J11-2 E18 Selects recording track for read or write operation. Logic 1 selects track A; Logic 0 selects Track B.
GND J11-3 E19 Return path for all analog and logic signals.
+5V
(input)
J11-4 E20 +5 V is passed to Servo Board at point E3.
DATA_OUT
(output)
J11-5 E21 Data output from drive to tape drive 6801. Data is encoded in bi-phase mark format as described in DATA_IN signal. Jitter in signal is specified at 4% maximum, peak shift at 5% maximum.
+12VL
(input)
J11-6 E22 +12 V is passed from R/W to Servo Board at point E15.
/WRENABLE
(input)
J11-7 E23 Selects write mode (Logic 0) or read mode (Logic 1) or R/W circuit operation (active low).
- J11-8 E24 No connection

2.4  Differences of Expansion Module #3

Expansion Module #3 is designed for the consumer who owns ColecoVision. It consists of the Memory Console, the keyboard, the printer, and various cords and cables to connect the components. The Memory Console attaches to the ColecoVision Console. The consumer provides his own TV. The major difference between Expansion Module #3 and the complete Adam Home Computer System is in the Memory Console. The equivalent of the CPU Board is housed in the ColecoVision Console, not in the Memory Console. Expansion Module #3 does not provide composite video output; therefore, a monitor cannot be used.

Expansion Module #3 is not packaged with "joystick" game controllers or the antenna switch box, since these items come with ColecoVision.

The ColecoVision Board and the Memory and I/O Board connect via two 30-pin ribbon cables, a dual 30-pin card edge connector, and the Interconnect Board, making a connection between J1 on the Memory and I/O Board and the expansion port of the ColecoVision console. Many of the connections are made pin-for-pin. The exceptions are:

A0-A15 These lines are buffered. The input to the buffer is from the ColecoVision, and the tristate control of the buffer (/ADDRBUFEN) is from the Memory and I/O Board.
D0-D7 These lines are buffered bidirectionally. The /RD signal from the ColecoVision controls the direction (when active, data flows toward the ColecoVision) and the /245EN signal controls the tristate function.
/IORQ This line is connected directly between the two boards (pin 55) and is also buffered (controlled by /ADDRBUFEN) and connected to pin 40 of the Memory and I/O Board.
F´ CLOCK This line, pin 40 of the ColecoVision Board, is connected to pin 45 of the Memory and I/O Board.
F CLOCK This line, pin 45 of the ColecoVision, is not connected.
/M1, /MREQ,
/RFSH, /WR,
/RD
These lines are buffered. The input to the buffer is from the ColecoVision, and the tristate control of the buffer (/ADDRBUFEN) is from the Memory and I/O Board.

3.  THE KEYBOARD

3.1  Theory of Operation

The keyboard is the major input device through which the user communicates with the system. The game controller joystick, buttons, and keypad can also be used to input information. The keyboard consists of two major subsystems. The external subsystem is an array of keys much like that of a mechanical typewriter. The internal subsystem, located on the Keyboard Printed Circuit Board, includes the keyboard 6801 microcomputer and the AdamNet serial interface.

The keyboard contains 75 full-travel keys, including special function keys. Some special function keys are labelled on the key top., for example, STORE/GET, DELETE, BACKSPACE. The function keys on the top row of the keyboard are Smart Keys, marked I through VI. Corresponding Smart Key labels shown on the video display identify their functions.

The keyboard 6801 determines which keys the user presses through the keyboard matrix. Every 5 or 8 milliseconds, the keyboard 6801 scans the matrix and stores the characters in a buffer.

The matrix consists of vertical columns which correspond to keyboard 6801 output lines, and horizontal rows which correspond to keyboard 6801 input lines.

A debounce function determines if any of the keys registers a low signal; then that row is read horizontally. More than one row in a column is read if more than one key in that column is depressed. The ASCII code for the depressed key or keys is read back to the 6801. The keyboard 6801 compares the code with the code input from the previous scan. If it is the same, the information is recorded; if it is different, the information is not recorded.

The keyboard 6801 responds to the following commands from the Master 6801:

3.2  Interconnects

The lines linking the keyboard 6801 to AdamNet are:

4.  THE PRINTER

4.1  Theory of Operation

The printer houses two printed circuit boards: the Printer Board and the Linear Power Supply Board. The Printer Board includes a 6801 microcomputer and parallel drivers that control the printer's electro-mechanical devices. The electro-mechanical devices include the daisy wheel motor, the carriage motor, the platen advance mechanism, the print solenoid, and the ribbon solenoid. The Linear Power Supply Board includes regulators, rectifiers, and a transformer. For more information on the power supply, refer to Chapter 2, Section 6.

4.2  The Printer Board

The printer 6801 communicates with the Master 6801 on the Memory and I/O Board via AdamNet to receive data to be printed, controls the motions of the printer's mechanical parts, and ensures that the printer performs the optimum number of motions simultaneously.

Within the printer 6801 RAM is a 16-character buffer for data being sent to the printer over AdamNet. The buffer ensures that time is not lost between characters being printed, and maximizes printing speed.

The printer 6801 responds to some ASCII control codes, including carriage return, line feed, backspace, escape, shift-out, and shift-in. Shift-out causes the printer 6801 to reverse its left and right directions, allowing printing from right to left.

The printer 6801 controls the printer's electro-mechanical devices. It also ensures that lateral carriage motion, rotation of the daisy wheel, and stepping of the platen can be activated simultaneously.

4.3.  Interconnects

The lines linking the printer 6801 to AdamNet are:

5.  GAME CONTROLLERS

The game controller contains an 8-position joystick, two push buttons, and a 12-key keypad. The information from a controller is read by the CPU on eight input lines through a single port. Once a port has been read, the input data must be decoded. See CONT_SCAN in the OS-7 Source Code Listing for details.

[FIGURE 2-5: CONTROLLER CONFIGURATION]

6.  POWER SUPPLY

6.1  Power Supply Voltage

The power supply for the ADAM computer is located in the printer. The power supply converts the incoming line voltage (AC) to one +18 V unregulated voltage that powers the ribbon solenoid, and fours low-level, regulated DC voltages as follows:

+5V Main source of power to the CPU.
-5V Supplies power to the CPU.
+12VI Supplies power to drive the inductive loads such as carriage motor, daisy wheel motor, print solenoid, platen motor, and digital data drive
+12VL Supplies power to the system logic.

6.2  Excessive Current Output Protection

The power supply uses a variety of methods to protect against excessive current output.

The AC line may vary from 180 VAC to 132 VAC. The power supply ensures a constant and quiet source of DC power.

6.3  Printer/Memory Console Interface Cable

The printer/console interface cable consists of 7 insulated wires and one uninsulated drain wire.

Pin Color Voltage/Description
1 Brown +12L VDC + 0.508 V
- 0.6 V
2 Red +12I VDC + 0.497 V
- 0.6 V
3 Orange +5.075 VDC + 0.079 V
- 0.255 V
4 Yellow -5.15 VDC + 0.25 V
5 Green Ground  
6 Blue AdamNet  
7 Violet Reset  
8 -- Drain  
9 -- No wire  

6.4  Power Supply Output to CPU (via Printer/Memory Console Interface Cable)

Voltage Full Load Current
+5V 2.75 A
-5V 0.2 A
+12VI 0.6 A
+12VL 0.3 A

6.5  Power Supply Output to Printer

Voltage Full Load Current
+5VL 0.25 A
+12VI 1.95 A
+18V (unreg) 1.0 A


CHAPTER 3: SOFTWARE

1.  INTRODUCTION

This chapter presents technical information on each of ADAM's software components.

2.  MEMORY MAP AND POWER UP/RESET PROCEDURE

Adam's Z80 microprocessor can address 64K bytes at any one time. The 64K addressable memory space is divided into two 32K sections. Each section may contain one of cour memory options. Any one option for lower memory and any one option for upper memory can be selected for the full 64K memory space via port 7FH.

Memory Options for 0 - 7FFFH (lower memory)

SmartWriter
Word Processor
ROM
32K
Intrinsic
RAM
32K
Expansion
RAM
OS-7 ROM
24K
Intrinsic
RAM

Memory Options for 8000H - FFFFH (upper memory)

 
32K
Intrinsic
RAM
 
32K
Expansion
ROM
32K
Expansion
RAM
32K
Cartridge
ROM

2.1  Lower Memory Options

SmartWRITER Word Processor ROM - This memory option consists of 32K of SmartWRITER ROM code. A small part of this code, EOS_BOOT, is responsible for system initialization during power up and reset. EOS ROM can also be accessed when this option is selected. See Subsection 4.1, EOS, for further details.

32K Intrinsic RAM - This option is the lower half of the 64K RAM included with every ADAM. DMA transfers to AdamNet can take place only in intrinsic RAM. SmartBASIC and most Programs stored on data pack reside in this memory.

32K Expansion RAM - This option is the lower half of the 64K Memory Expander, an optional feature not included with the ADAM system. The 64K Memory Expander increases ADAM's memory to 144K of read/write memory (64K intrinsic, 64K expansion, 16K VRAM).

OS-7 and 24K Intrinsic RAM - This option contains OS-7 and 24K of ADAM's intrinsic RAM. OS-7 is the 8K ROM installed in ColecoVision and ADAM. In Expansion Module #3, this ROM is in the ColecoVision. The description of the 32K Intrinsic RAM also applies to this 24K intrinsic RAM.

2.2  Upper Memory Options

32K Intrinsic RAM - This option is the upper half of the 64K intrinsic RAM included with ADAM. DMA transfers to AdamNet can take place only in intrinsic RAM. SmartBASIC and most programs stored on data pack reside in this memory.

Expansion ROM - This memory is provided by an expansion ROM, an optional feature not included in the ADAM system. The expansion ROM is installed in Connextor #2 on the Memory and I/O Board. EOS_BOOT checks this connector for valid data before initializing EOS. If valid data is found, the EOS_BOOT code jumps to this ROM.

32K Expansion RAM - This is the upper half of the optional Expansion RAM described for lower memory.

32K Cartridge ROM - This memory option is the cartridge slot on ADAM or ColecoVision, used to execute game cartridges or other cartridge-based software.

2.3  Power Up/Computer Reset Procedure

When Adam powers up or when the computer reset switch is pressed, the MIOC selects SmartWRITER in lower memory and Intrinsic RAM in upper memory. EOS_BOOT executes this procedure:

  1. Check for Expansion ROM. If Expansion ROM exists, jump to Expansion ROM.

  2. Else, initialize EOS and jump to EOS_START.

  3. Check for the presence of devices in this order:

  4. If a device exists, check for valid data in the device.

  5. Boot and execute code from the first valid device found by loading block 0 to address 0C800H, then jumping to 0C800H.

  6. If no valid data is found on any device, execute SmartWRITER.

2.4  Z80 I/O Port Assignments

Port Description
00H through 1DH Reserved
1EH Optional Auto Dialer
1FH Reserved
20H through 3EH Reserved
3FH* Network reset; EOS enable
40H through 4EH Reserved
4FH Expansion Connector #2
50H through 5DH Reserved
5EH Optional Modem Data I/O
5FH Optional Modem Control Status
60H through 7EH Reserved
7FH Memory Map Control
80H through FFH Reserved for ColecoVision use

*Net reset - The net reset function is performed by setting bit 0 and then resetting bit 0.

*EOS enable - setting bit 1 enables the EOS ROM. Resetting bit 1 disables EOS ROM. The EOS enable function affects only the SmartWRITER ROMs. To access the EOS ROM, the SmartWRITER ROMs must be selected.

For further details on port assignments, see PORT_COLLECTION in the EOS Source Code Listing.

2.5  Memory Map Control

Software can select the memory configuration by writing to Port 7FH. Data bits D0 and D1 selecte the lower (0 - 7FFFH) memory option. D2 and D3 select the upper (8000H - FFFFH) memory option. D4 through D7 are reserved for future expansion, and should remain as 0. The value to be written to Port 7FH is obtained from the following tables.

Lower Memory Option Selection

D1 D0 Description
0 0 SmartWRITER ROM and EOS ROM
0 1 32K Intrinsic RAM
1 0 32K Expansion RAM
1 1 OS-7 + 24K Intrinsic RAM

Upper Memory Option Selection

D3 D2 Description
0 0 32K Intrinsic RAM
0 1 Expansion ROM
1 0 32K Expansion RAM
1 0 Cartridge ROM

2.6  Reset Procedures

Adam can be reset in either computer mode or in game mode. When the computer reset switch is pressed, Adam resets to computer mode, according to the power up procedure described in Subsection 2.3.

When the cartridge (or ColecoVision) reset switch is pressed, Adam resets to game mode. 32K of Cartridge ROM are switched into upper memory. OS-7 plus 24K of intrinsic RAM are switched into the lower bank of memory.

3.  ADAMNET

3.1  Introduction

AdamNet is based physically on a shared bus, single master topology, although logically it resembles a token-passing network. The physical design of the network is depicted in Figure 3-1.

[FIGURE 3-1: BUS NETWORK]

The circles represent nodes (for example, printers or keyboards), which connect to a shared bus, represented by the horizontal line. The network is a four-wire bus. The wire definitions are:

The network resides in all Adam components. The reset line behaves as a master reset signal to every node attached to the network. A transition on this line causes all attached devices to enter the power-on state, allowing the master to bring sanity to the network during periods of erratic behavior.

3.2  Logical Design

Logically, AdamNet resembles a token-passing network. In a token-passing network, the right to talk on the bus is passed from node to node. This right, or "token", allows the node to access the bus and send messages. One node functions as the master of the bus. The master gives the token to other nodes with a regulated frequency.

4.  OPERATING SYSTEM

4.1  EOS (Elementary Operating System)

This section provides information to allow designers to write programs that operate in a Adam/EOS environment. It describes the organization of the Elementary Operating System (EOS), including file management and executive calls.

The Elementary Operating System is a collection of service routines that provide input/output facilities to peripheral devices. Programs accessing these devices need not be conceened with the physical characteristics of the devices, because EOS logically resides between the physical devices and application programs. EOS shields application programs from the details of AdamNet.

FIGURE 3-4: EOS MEMORY MAP

FILE CONTROL BLOCK HEADERS D390H
FCB BUFFERS (3 x 1KB) D400H
EOS CODE E000H
ADAMNET DEVICE DRIVERS F400H
EOS DATA TABLES FBFFH
EOS JUMP TABLES FC30H
GLOBAL RAM AREA FD50H
PROCESSOR CONTROL BLOCK FEC0H
DEVICE CONTROL BLOCK FEC4H
DMA RESERVED BYTE FFFFH

4.1.1  EOS Overwrite Addresses

Some applications may not require all of the routines provided by EOS. To accommodate this situation, EOS has three defined starting locations. Applications should always access the routines from the defined jump table locations.

Location 0D390H is the lowest EOS starting address. File manager software is loaded in this part of EOS. If the application program uses file manager software, the application should not overwrite 0D390H or above.

Location 0E000H. If the application does not use the file manager software, it can overwrite EOS up to 0DFFFH. Routines that access the lower level network device drivers, and the device drivers for the VDP, controllers, and sound generator are available.

Locations 0F400H to 0FC30H contain the lowest level device drivers for AdamNet. The application can extend up to 0F3FFH if it is using OS-7 or its own drivers for the VDP, controllers, and sound generator.

4.1.2  EOS Files

The file structure takes advantage of the sequential design of the data pack. (For more information on tapes and tape formats, see Chapter 3, Section 5.) A file directory keeps track of the location of files on tape, and other pertinent information such as size, creation date, and protection attributes. Some programs, such as Super Games, do not require directories.

Data is stored on tape in blocks of 1K (1024 bytes). An EOS file occupies a number of contiguous blocks, allocated upon file creation. EOS files can be any number of blocks, but are limited by the physical storage space available.

Block 0 is reserved for a cold start loader. Block 1 and up, depending on the directory size, contain the directory.

The EOS file manager accesses and controls a file through a File Control Block (FCB) maintained in RAM. The FCB contains static and dynamic information about the file. THe FCB is created when a file is opened and destroyed when the file is closed. Application programs are limited to two FCBs at any one time. Each FCB is 36 bytes long. A data buffer, 1024 bytes long, is associated with each FCB.

5.  TAPE FORMAT AND OTHER TAPE CONSIDERATIONS

There are two types of tape format for ADAM data packs. Type GW tapes have block 0 at the end. Type HE tapes have block 0 in the middle. An example of a type GW is the Buck RogersTM Planet of ZoomTM Super Game. Both SmartBASIC and the blank data pack are examples of type HE tapes.

The capacity of the tape is 256K. Blocks are defined as 1K in length. There are two tracks, 128 blocks per track. Block numbers refer to the block of data on a data pack referenced by application software. The following illustration shows physical block positions.

FORMAT GW (Block 0 at the end)
<---- tape motion
0                     40                 7F block no.
=========================================== track 0

=========================================== track 1
80                    C0                 FF block no.
FORMAT HE (Block 0 in the middle)
<---- tape motion
40                   7F 0                3F block no.
=========================================== track 0

=========================================== track 1
80                   BF C0               FF block no.

5.1  Considerations in Choosing Tape Format

Type GW tapes do not contain a directory. Type GW tapes cannot be readily copied, so users are not able to easily copy one GW tape to another GW tape.

Type HE tapes are compatible with other type HE tapes. If a program needs to store information on a separate data pack, access or be accessed by other software, then a type HE tape is suggested.

6.  SmartWRITER

6.1  Memory Map

EOS_BOOT 0 INT. VECTORS 0
100H HI_AUX_ACCESS_
ROUTINES
100H
HI_AUX_DATA_
BUFFER
400H
ROM
32K
WORD PROCESSOR
PROGRAM
7FFFH Low
Intrinsic
RAM
32K
TEXT 800H


7FFFH
WP RAM 8000H 8000H
CURRENT_WINDOW 8488H
WP RAM 9108H
UNDO_WINDOW 919AH
WP RAM 9E1AH
High
Intrinsic
LOW_STACK 9E2AH High
Expans.
RAM
32K
HIGH_STACK A26AH RAM
32K
PUT/FETCH
LOW (AUX) MEM
A6AAH
WORD PROCESSOR
RAM
A7C9H

D38FH
EOS D390H

FFFFH
FFFFH

6.2  SmartWRITER-Compatible Files

Files must meet certain criteria to be compatible with SmartWRITER. SmartWRITER files have the user file attribute bit set, and the last character of the file name is H. SmartWRITER files start with a header, and ASCII information begins after the header. The first two bytes of the file define the length of the header. The third byte contains the application code (1 for SmartWRITER). The format of the header is determined by the application code. Backup versions of SmartWRITER files have a lower-case "h" as the file type.

An example of a SmartWRITER file follows:

Byte Description
0 HEADER_SIZE_LOW (=0)
1 HEADER_SIZE_HIGH (=1)
2 FILE_TYPE_CODE (=1)
3 TOP_MARGIN
4 BOTTOM_MARGIN
5 LEFT_MARGIN
6 RIGHT_MARGIN
7 LINE_SPACING
8 TAB_ARRAY(1) [0 = NO MRG, 1 = MRG]
   
89 TAB_ARRAY(80) [0 = NO MRG, 1 = MRG]
90 UNUSED
   
258 UNUSED
259 FIRST ASCII DATA BYTE
   
n ASCII DATA

7.  SmartBASIC

SmartBASIC is generally source-code compatible with Applesoft BASIC. PEEKs and POKEs, and other machine-dependent features of Applesoft BASIC, are different in SmartBASIC. SmartBASIC graphics feature four modes:


CHAPTER 4: [unknown; not present]


CHAPTER 5: DEVELOPMENT TOOLS AND UTILITIES

1.  SUPER GAMES

This section explains background loading, tape mapping, and playability of Super Games and other programs that use OS-7. Familiarity with OS-7 is assumed. The information and examples in this section should help programmers who are accustomed to cartridge software adapt to tape-based software more easily.

1.1  Background Loading

The background loading software (see Subsection 1.7) is designed to load overlays from data pack to RAM while the program is executing. Care must be taken that data being loaded during execution does not destroy data that is controlling execution. A good approach is to use two buffers. One buffer is loaded while the other is controlling program execution.

1.2  Timing Considerations

Each background block read takes about one second, assuming no retries and no repositioning. Retries take about 1.2 to 1.4 seconds and happen only if the checksum fails to compare on read. There are a maximum of three attempts to read a block on the tape, then the checksum failed code is sent. Repositioning takes as long as one second to find the current position on tape (approximately one second for every 80 inches of tape travel). Repositioning is automatically handled by the drive. For the NMI-driven tape manager, additional overhead in transfer time averages 8 msec (one-half of a 60 Hz clock tick). Buffering data for transfer to VDP RAM results in Z80 CPU usage, assuming use of WRITE_VRAM. The following table shows the Z80 CPU time used in VDP RAM writes.

TABLE 4: Z80 CPU TIME FOR VDP RAM WRITES

Number of bytes to transfer Time (msec)
1 0.077
10 0.175
100 1.16
1000 11.25
2000 22.4
4000 44.8
8000 89.6

1.3  Mapping

The programmer must lay out the data to minimize load time, through mapping. Minimizing load time is the most crucial aspect of designing Super Games.

Since the data on tape is a memory image, it may be read directly into Z80 RAM and immediately executed. The programmer should diagram the tape blocks on a time line, following the timing considerations in Subsection 1.2. Some action on the screen must hide the loading process. Rewinding and positioning time must be included in calculating load size and load time.

An example of a time line diagram follows. It shows the screen actions and what is loaded in background while the action is taking place.

FIGURE 5-1: TIME LINE DIAGRAM

Time in
Seconds
Screen Loading Address Block
Number
0
1
2
3
BLANK COLD START
MAIN
C800H
8000H
8400H
8800H
0
1
2
3
4
5
6
7
TITLE SCREEN OVERLAY 3 8C00H
9000H
9400H
9800H
4
5
6
7
8
9
10
11
LOGO SCREEN   9C00H
A000H
A400H
A800H
8
9
10
11
12
13
14
15
SELECT OPTIONS   AC00H
B000H
B400H
B800H
12
13
14
15
16
17
18
19
GAME START  
[rewind to Track 1 Sector 1; 5 seconds of rewind time follow]
BC00H 16
128
20
21
22
23
   
 
OVERLAY 4
C000H
C400H
129
130
24
25
  ETC... C800H
CC00H
131
132

1.3.1 Overlay Control Blocks

To read memory images into RAM, three pieces of information are required. They are:

This information is organized into a 5-byte block called an Overlay Control Block (OCB). The Overlay Control Blocks are organized into an Overlay Control Table (OCT). The OCT controls the loading of data from tape using the tape interface software described in Subsection 1.6. The table should be pointed to by a two-byte pointer and it should be terminated by a byte set to FFH. The Overlay Control Table should be loaded immediately after the cold start loader.

1.4  Start of Game

EOS loads Block 0 (the cold start loader) to C800H and passes control to it. The cold start loader then initializes the system and loads enough of the main program to allow some user interaction to begin. The following rules define the interface to the cold start loader.

  1. The main program is loaded to location 8000H.

  2. Immediately following the ColecoVision OS vectors at 8000H, and the game name, is a pointer to the OCT. The first entry in the OCT describes the main program.

  3. Control is passed to the main program by the vector at address 800AH as defined in the OS-7 PRIME.

  4. The main program must contain the OCT in the first 1K block.

  5. The main program must contain the background loading routines described in Subsection 1.7. They are required to reside in the first 3K.

  6. The main program must immediately display graphics or allow some user interaction.

  7. Once control is passed to the main program, game play must start as soon as possible.

  8. When control is transferred to the main program, Register B contains the boot device ID. Register B should be stored at the globally-defined address DEVICE_ID.

Subsection 1.5 is an example of the 8000H area code which interfaces to the cold start loader. Compare this to the area defined in OS-7.

1.5  8000H Area Code - Interface to Cold Start Loader.

Tape Interface Software

The tape interface software loads RAM from tape in background using the OCT structure defined in Subsection 1.7. The entry points for these modules are described in the following subsections. The tape manager programs are interrupt-driven and should be called on every clock cycle (60 Hz) to drive background loading. The OCT, DDP_MANAGER (Subsection 1.10) and TAPE_INTERFACE (Subsection 1.9) or DDP_INTERFACE (Subsection 1.11) must be linked into the program.

1.6.1  Tape Manager Programs

The tape manager consists of two interchangeable parts dependent upon environment.

TAPE_MANAGER

The program TAPE_MANAGER (shown in Subsection 1.8) is designed for use on the HP64000. This program allows for simulated tape I/O via the HP disk, and should be used in conjunction with TAPE_INTERFACE.

DDP_MANAGER

This program, shown in Subsection 1.10, replaces the tape manager in working games. Entry points and interface are identical to the TAPE_MANAGER except that this module uses EOS calls to manipulate the tape. DDP_MANAGER should be used in conjunction with DDP_INTERFACE.

The final version of the game should have the DDP_MANAGER installed. The tape managers are fully interchangeable.

1.6.2  TAPE_INTERFACE

TAPE_INTERFACE consists of a set of entry points and data passed in the accumulator. DDP_INTERFACE is similar to TAPE_INTERFACE, except that some labels are different.

Entry Points Accumulator Comments
LOAD_OVERLAY OVERLAY_NUMBER The code uses the overlay number to look up OCT information. The overlay is loaded from tape to Z80 RAM.
WRITE_OVERLAY OVERLAY_NUMBER As in LOAD_OVERLAY, but data flow is from RAM to tape.
ABORT_TAPE -------- Aborts all tape functions. Resets tape. Makes tape ready to immediately receive new commands. Does not reposition tape.
TEST_TAPE -------- Returns status of tape.

Status from TEST_TAPE may show the following conditions:

0 OK
1 Checksum failed
2 Block not found
3 Tape not present
4 Device not present

The checksum shows that after three retries, the tape block was not read correctly and the data transferred by the read command is not valid.

1.7  Background Loading Software

1.8  TAPE_MANAGER

1.9  TAPE_INTERFACE

1.10  DDP_MANAGER

1.11  DDP_INTERFACE


APPENDIX

1.  Keyboard Table

2.  ADAM Emulation Considerations

ADAM hardware characteristics affect the selection and interface of an emulator for ADAM.

ADAM has dynamic RAMs that must be refreshed to maintain integrity. The RAMs require an 8-bit refresh. Since the Z80 performs a 7-bit refresh, the eighth bit is manufactured by the MIOC, using other signals from the Z80. In general, the signals are:

The master 6801 performs a direct memory access into the 64K intrinsic RAM addressed by the Z80. The MIOC is responsible for the setup and execution of DMA by the Master 6801.

Some emulators place a load on the clock circuit that drives the Z80. Problems with an interface to an emulator my require a check of the clock and a modification to R60 on the CPU Board.

3.  PROGRAM CAUTIONS - NMI (NON-MASKABLE INTERRUPTS)

3.1  Deferral

Due to the hardware configuration of ADAM, certain routines which write to VRAM, (e.g., WRITE_VRAM (OS-7)), could have unpredictable results if they are interrupted during execution by an NMI and the VRAM is accessed by the interrupt handling routine.

One possible solution to this problem is a defer interrupt routine. The function of this routine is to hold off (defer) the servicing of the interrupt until the current VDP access routine is finished.

The reason for a defer interrupt routine is to prevent the VDP's internal auto-incrementing address counter from being re-adjusted by an interrupt routine that also wants to access the VDP.

Interrupt deferral is not necessary if the VDP is not accessed by the interrupt handling routine.

3.2  Bank Switching

The NMIs are vectored automatically to 66H by the Z80. If the NMI generated by the VDP occurs when there is no handling routine set up at 66Hm the computer will lose control. Be sure to turn off the VDP interrupt output before doing a memory bank switch to lower expansion RAM if no routine has been set up previously in the expansion RAM to handle the NMI.

If OS-7 is bank-switched in, the NMI service is directed to location 8021H, where there must be a routine to maintain program control if the NMI is active.

4.  Schematics and Component Location/Identification Drawings

4.1  Memory and I/O Board

4.1.1  Memory and I/O Board Schematic (Sheet 1)

4.1.2  Memory and I/O Board Schematic (Sheet 2)

4.1.3  Memory and I/O Board Component Location/Identification Drawing

4.2  CPU Board

4.2.1  CPU Board Schematic

4.2.2  CPU Board Component Location/Identification Drawing

4.3  Interconnect Board

4.3.1  Interconnect Board Schematic

4.3.2  Interconnect Board Component Location/Identification Drawing

4.4  Linear Power Supply

4.4.1  Linear Power Supply Schematic

4.4.2  Linear Power Supply Component Location/Identification Drawing

4.4.3  Linear Power Supply Sub-Assembly


SECTION II

EOS USER'S MANUAL


SECTION III

OPTIONAL PERIPHERALS


-DISK DRIVE-

Formatting

The ADAM disk can be formatted by using the Disk Manager software included with every production disk drive. The ADAM disk format is single sided, double density.

The Digital Data Pack tape can't be formatted by the user.

Storage Capacity

The formatted ADAM disk holds 160Kbytes of data. The blocks are numbered sequentially 00H through 9FH. The ADAM Digital Data Pack tape is formatted for 256Kbytes in blocks numbered sequentially from 00H through FFH.

AdamNET Device Number

After pressing the computer reset, if block 00H can be accessed and loaded to C800H from one of the drives, register B of the Z80 and memory location DEFAULT_BT_DEV will contain the boot device number before program control is directed to C800H.

-ADAMLINK MODEM-

The following source code listing is the low level drivers used for the AdamLink MODEM. This is all the information necessary to interface with the AdamLink MODEM.


SECTION IV

EOS-6 ABSOLUTE LISTINGS



SECTION V

OS-7 ABSOLUTE LISTINGS